Increasing signaling speeds in circuit boards presents new challenges in signal integrity requirements. A signal conductor with a resistance of ten to twenty ohms at zero hertz may display a much higher effective resistance when the signal transmission speeds reach ten gigahertz or higher. This higher effective resistance comes about due to the phenomenon of skin effect, in which current tends to concentrate at the surface or “skin” of the signal conductor as signal speed increases. With high-speed signaling, the effective cross-sectional area of the signal conductor which is conductive is decreased, leading to increased resistance, heating and signal attenuation.
Signal integrity issues become even more pronounced where high speed signals are driven over signal conductors of increasing length. When the propagation delay through a signal conductor becomes significantly higher than the rise time of the signal, signal reflections that degrade signal integrity appear in the signal conductor as an undershoot or overshoot. With increasing signaling speeds and decreasing rise times, minimizing propagation delay and reflections becomes an issue in maintaining signal integrity.
One method of minimizing propagation delay is to simply minimize the length of signal conductors. FIG. 1 is a simplified block diagram of a typical programmable logic circuit 1 in the prior art. A printed circuit board (PCB) 2 supports four Field-Programmable Gate Array (FPGA) chips 3-6 and two conductive connector circuits 7-8. PCB is less than one inch on a side. Three signal conductors 9-11 supported by the PCB are also illustrated. Signal conductor 9 connects pad 12 at conductive connector circuit 7 and pad 13 at FPGA 3. Signal conductor 10 connects pad 14 at FPGA 3 and pad 15 at FPGA 4. Signal conductor 11 connects pad 16 at conductive connector circuit 7 and pad 17 at FPGA 6. Signal conductors 9-11 conduct signals at speeds of ten gigahertz or greater, with corresponding rise times of around thirty picoseconds.
FIG. 2 is a simplified cross-sectional view of signal conductor 9 of FIG. 1. The cross-sectional view shows example signal conductor 9 supported by the PCB 2. A conductive copper strip 18 has a width of twelve microns and a thickness of two microns. An insulating layer of dielectric 19 separates the conductive copper strip 18 from the PCB 2. An additional layer of dielectric 20 with a thickness greater than that of the conductive copper strip 18 surrounds and covers the conductive copper strip 18.
FIG. 3 is an expanded cross-sectional diagram of the conductive copper strip 18 of FIG. 2 illustrating skin effect at high signal frequencies. Arrows 21 indicate the skin depth at which current concentrates near the upper surface of conductive copper strip 18 during high-speed signaling. Arrows 22 indicate the skin depth at which current concentrates near the lower surface of conductive copper strip 18 during high-speed signaling. Arrows 23 and 24 indicate the skin depth at which current concentrates near the vertical edges of conductive copper strip 18 during high-speed signaling. Patterned area 25 indicates the effective cross-sectional conductive area of the conductive copper strip 18 due to skin effect.
Referring again to FIG. 1, the length of signal conductors 3-6 as illustrated is typically less than twenty millimeters. Where signal transmission lines of twenty or more millimeters in length are required, chip designers will employ techniques such as termination and rebuffering to avoid signal reflections and maintain signal integrity. In some cases, however, it is desirable to drive high-speed signals along signal transmission lines of lengths much greater than twenty millimeters, and without the use of rebuffering or termination. For these longer transmission lines, it is desirable to minimize the increases in resistance due to skin effect. A technique is therefore sought for providing a signal conductor with increased surface area.